Why Memory Bandwidth, Not Raw Compute, Defines Maia 300
Maia 300's headline spec isn't a FLOPS number - it's memory. The chip splits its work across multiple chiplets: a main compute die manufactured on TSMC's N2P process, paired with separate memory-controller and I/O chiplets built on a more mature 3nm node [1]. Wrapped around that compute core are eight stacks of HBM4 memory totaling 288GB, delivering up to 18 TB/s of peak bandwidth, all inside a 950-watt power budget per accelerator [2]. That's a 2.5x jump in memory bandwidth and 33% more capacity than the Maia 200 that shipped earlier in 2026, even though raw compute only grew a comparatively modest 36% to roughly 13.8 petaflops at FP4 precision and 6.9 petaflops at FP8 [2][3].
The reason memory gets the bigger upgrade is that inference, especially the kind involved in long-context reasoning and multi-step agent workflows, is bottlenecked less by how fast a chip can multiply matrices and more by how quickly it can move a model's parameters and conversation context in and out of memory during the token-by-token 'decode' phase. Futurum Research's Brendan Burke describes Maia 300 as built from the ground up for exactly that profile: 'long-context, reasoning-intensive, decode-heavy inference' [4]. In other words, Microsoft isn't chasing Nvidia on a generic compute benchmark - it's optimizing for the specific shape of workload that Copilot, GitHub Copilot, and OpenAI's models actually generate in production.


