TSMC's AI-Driven Capacity Expansion and Earnings Surge

TSMC's C.C. Wei told investors that packaging capacity, not wafer capacity, is now the binding constraint on customer growth ^[1]. In his words: "Our packaging capacity is so tight that now it's limiting my customers' growth. We welcome that additional flexibility" ^[1]. That framing lines up with the shape of the new $100 billion Arizona commitment itself: the expansion adds at least four more fabs plus dedicated advanced packaging facilities ^[2], and analysts describe CoWoS - the process that binds AI processors to high-bandwidth memory - as the industry's real chokepoint, ahead of raw fab output ^[3]. The node-mix data underscores how early the wafer side of that ramp still is: 2-nanometer shipments were just 3% of Q2 wafer revenue even as two of the four new Arizona fabs are slated to run 2nm-class nodes ^[2].

TSMC did not just beat estimates - it raised both its 2026 capex guidance, to $60-64 billion from $52-56 billion, and its revenue growth outlook, to above 40%, in the same earnings call ^[2]. Commentary around the earnings coverage drew a pointed contrast with Samsung's own quarter, where a large profit jump still triggered a share slump, framing TSMC's simultaneous raise as close to the cleanest available read on real-world AI hardware demand, given that TSMC manufactures for Nvidia, AMD, Apple and Broadcom alike. That reading lines up with how analysts characterized the demand itself. Omdia's Simon Chen argued the current cycle is different in kind from past speculative run-ups: "The demand we see is structural, backed by massive, tangible capital expenditures from hyperscalers" ^[4]. Counterpoint's William Li largely agrees that demand is exceptionally strong, but notably locates the risk on the supply side rather than the demand side ^[4].

Because ASML remains the sole global supplier of EUV lithography systems, its capacity roadmap effectively caps how fast TSMC, Samsung and Intel can add advanced-node capacity, regardless of how much capex those chipmakers commit. ASML's own Q2 2026 results - €9.3 billion in net sales and 54.0% gross margin, both ahead of guidance - reflect that leverage, and the company raised its full-year outlook to €43-45 billion in sales on the back of what it called extremely strong order intake tied to AI investment across Logic and Memory customers ^[5]. Crucially, ASML is planning to expand EUV capacity by 30% for 2027 versus its 2026 base of roughly 65 systems, with a further 30% increase under investigation for 2028 ^[5]. Market watchers pointed to a concrete sign of that demand this quarter: ASML sold 16 of its most advanced EUV lithography machines in Q2 alone. Community discussion of ASML's tool economics (advanced EUV systems running well over $300 million apiece) helps explain why that expansion, not TSMC's or ASML's headline capex figures alone, may be the tighter constraint on how quickly the industry's AI capacity can actually grow.

Despite the record results and the raised guidance, TSMC shares slipped in the days around the report - a reaction market commentary attributed to expectations already being priced in rather than to any weakness in the underlying numbers. The skepticism has a margin-side justification: Counterpoint's William Li flagged that EUV supply constraints and overseas fab investment could weigh on TSMC's margins near term ^[4], and the aggressive N2 ramp is expected to dilute second-half gross margin by roughly three to four percentage points ^[4]. That tension between headline growth and margin drag is compounded by the sheer scale of the new spending commitment - $60-64 billion in 2026 capex alone ^[2]- which investors have to weigh against near-term profitability. Retail investor discussion floated a second, unrelated explanation for the drop: rotation pressure from a resurgent Chinese memory-chip competitor entering the market, rather than anything specific to TSMC's own numbers. At the same time, community breakdowns of fab and EUV tool costs (roughly $10 billion per fab, plus $300 million-plus per advanced lithography system) argued the $100 billion Arizona figure is grounded in real unit economics rather than a speculative round number, pushing back on the idea that the spend itself is the problem.

TSMC's Arizona commitment has compounded steadily: $12 billion in 2020 ^[6], $40 billion by the end of 2022 ^[6], past $65 billion alongside a preliminary CHIPS Act agreement in 2024 ^[7], $165 billion after a further $100 billion pledge in March 2025 ^[8], and now $265 billion following this quarter's additional $100 billion commitment ^[9]. That trajectory is widely framed, including in community discussion, as a geopolitical hedge against a disruption in Taiwan - a concern with real weight given that Taiwan still produces more than 90% of the world's most advanced semiconductors ^[3]. But the hedge comes with a caveat raised in that same discussion: Arizona's fabs reportedly still cannot operate fully independently of TSMC's Taiwan headquarters and know-how today, meaning the buildout reduces geographic concentration in dollars committed well before it reduces operational dependency on Taiwan itself.