The 2nm process and quad-die architecture leap
Apple's M6 is the first Apple silicon chip built on TSMC's 2-nanometer (N2) process, debuting in a redesigned Mac mini with a 12-core CPU, a 12-core GPU carrying a Neural Accelerator in every core, and a new Dual 16-core Neural Engine [1]. Memory bandwidth reaches up to 170GB/s - a modest 10% bump over M5, though 2.5x the original M1 [1]. The bigger structural story is M5 Ultra, Apple's first quad-die design: two dual-die M5 Max chips fused through Apple's UltraFusion interconnect, which now carries over 4.4TB/s of bandwidth between the four dies so they behave as one processor [2]. That architecture scales to a 36-core CPU, an 80-core GPU, and up to 512GB of unified memory at 1.2TB/s of bandwidth - 50% more than M3 Ultra [3]. Notably, Apple stuck with TSMC's base N2 node rather than the newer, pricier N2P node, reportedly to lock in supply and control manufacturing costs - trading away roughly a 5% node-level performance and power edge for a more secure, cost-controlled 2nm supply chain [4].



