AMD acquires Taalas, betting on chips with AI models etched into silicon

Taalas does not build a general-purpose processor and load a model onto it afterward. Its model-specific integrated circuits, or MSICs, etch a model's weights and dataflow directly into the transistors and metal layers of the chip itself, replacing the external high-bandwidth memory GPUs rely on with an on-die Mask-ROM fabric for weights and an SRAM fabric for KV-cache and fine-tuning adapters ^[1]. The company's HC1 test chip, an 815 square millimeter die built on TSMC's 6-nanometer process with 53 billion transistors, runs in a 2.5-kilowatt server configuration ^[2]and served Meta's Llama 3.1 8B model at close to 17,000 tokens per second, a speed Taalas said was 48 to 73 times the throughput of Nvidia's H200 and B200 GPUs at a fraction of the power draw ^[12]. Independent testing by analyst Karl Freund of Cambrian AI measured throughput at 14,357 tokens per second on the same chip, close to Taalas's own reported number ^[4]. The tradeoff is rigidity: once a chip is fabricated for one model, it cannot be reprogrammed for another. Taalas says updating to a new model only requires changing about two of the more than 100 metal layers on the die, cutting a full respin down to roughly a two-month tapeout rather than a from-scratch redesign ^[1], but every model swap still means new silicon, not a software update.

The Taalas deal is AMD's third AI acquisition in nine months, following the November 2025 purchase of MK1 and the June 2026 acquisition of memory-optimization startup Mext ^[3], and it lands about seven months after Nvidia's own 20 billion dollar purchase of Groq's inference chip assets, its largest deal on record ^[5]. Where Groq's chips are model-agnostic and can run different models with low latency, Taalas goes the opposite direction: one chip, one model, maximum efficiency, zero flexibility. Trade press framed the acquisition as evidence that the industry expects inference architecture to become heterogeneous, with programmable GPUs handling training and prefill, the compute-heavy step of processing a prompt, while specialized chips like Taalas's handle latency-sensitive decode, the token-by-token generation step; that framing is trade-press analysis rather than a division of labor AMD itself has spelled out ^[1]. AMD said it plans to pair Taalas's chips with Instinct GPUs in system-level deployments alongside its Helios rackscale systems, EPYC CPUs and ROCm software stack ^[6]. Markets reacted mildly positively: AMD shares rose about 1.5 percent to roughly 489 dollars on the day of the announcement ^[7], and one investor-focused online community estimated the deal's value at 400 to 500 million dollars based on Taalas's roughly 200 million dollars in prior funding, an estimate AMD has not confirmed. AMD is not alone in chasing model-baked silicon: OpenAI unveiled its Jalapeno inference chip built with Broadcom in June 2026 ^[8], and Google is reportedly developing a 'Frozen v2' chip that etches part of Gemini's architecture into silicon while keeping weights updatable, targeting 6 to 10 times more tokens per watt than current TPUs ^[9].

Taalas was founded in 2023 in Toronto by a team with deep AI-silicon pedigree, led by chief executive Ljubisa Bajic, who previously led rival AI chip startup Tenstorrent ^[10]. The company raised roughly 219 million dollars across its funding history, including a 169 million dollar Series D in February 2026, with Fidelity Investments, Quiet Capital and investor Pierre Lamond among the lead investors across its funding rounds, on top of earlier rounds ^[11]. Reaction on hardware-focused forums has split along an unexpected axis: rather than debating the chip's merits, one active discussion reframed the deal as a case study in Canadian tech brain drain, noting that although Taalas was headquartered in Toronto, the overwhelming majority of its funding came from U.S. investors, and comparing it to ATI, the Canadian graphics company AMD acquired two decades ago whose Radeon division still operates out of Markham, Ontario. For AMD, the deal reads as much as a talent acquisition as a technology one: Bajic's team brings direct experience building specialized AI silicon outside the GPU paradigm that AMD did not have in-house before this deal ^[10].

Not everyone is convinced the etched-silicon approach scales, and the pushback splits into two distinct critiques. The technical critique, which circulated among hardware analysts on Reddit, argued that baking weights into silicon made the most sense when context windows were small, under roughly 4,096 tokens. Modern frontier models routinely handle context windows of 128,000 tokens up to over a million, and the KV-cache reads that dominate runtime at that scale are dynamic, per-conversation data that cannot be hardwired into a chip the way static weights can. If KV-cache access, not weight access, is what actually bottlenecks inference at long context lengths, etching weights into silicon solves a shrinking share of the real workload as context windows grow, and critics also pointed out that the HC1 test chip already needs aggressive quantization just to fit an 8-billion-parameter model onto its die. A separate, organizational critique came from a widely-viewed video breakdown of the deal, which framed it less as AMD buying a finished product and more as AMD adding to its silicon-design team, then raised a genuinely different open question: whether an ultra-specialized, single-model chip actually fits into AMD's existing GPU-centric portfolio, or whether it risks staying a niche addition alongside Instinct's general-purpose accelerators rather than becoming a core product line. Other video commentary was more measured, describing Taalas as a real speed-versus-flexibility tradeoff rather than a GPU killer, and cautioning that 'GPUs are so over' takes are premature. Taalas's own roadmap anticipates the scaling question on the technical side: its unannounced next-generation HC2 chip targets around 20 billion parameters per chip, with the company suggesting that around 50 accelerators chained together could theoretically support a trillion-parameter model ^[1], an architecture nobody has yet built or benchmarked at that scale, and one that still would not resolve the portfolio-fit question raised separately.